Change ENOMEM into EINVAL, since at this point memory allocation
errors don't occur, and bitstream decoding errors are not fatal.

Unref data after decoding failure to prevent re-entering the loop
with the same data.

This patch adds optional support for Arm Pointer Authentication Codes.

PAC support is turned on or off at compile time using additional
compiler flags. Unless any of these is enabled explicitly, no additional
code will be emitted at all.

Fixes inconsistent output frame count depending on --threads=X value
for the sample in #244.

Prevents dav1d_get_picture() from returning EAGAIN when no frame delay was
requested (threads=1, or threads > 1 and max_frame_delay=1).

Signed-off-by: James Almer <jamrial@gmail.com>

Ronald S. Bultje authored 3 years ago and James Almer committed 3 years ago

Right now, --alllayers 0 will only output operating points that exactly
match the largest one in the sequence header. However, in certain cases,
the largest one might not be available, and a smaller one should be
returned to the user instead.

This matches update_frame_buffers() in aomdec to output only the latest
frame if --alllayers 0 is specified.

Signed-off-by: James Almer <jamrial@gmail.com>

Henrik Gramner authored 3 years ago and Henrik Gramner committed 3 years ago

Avoids issues when dynamically linking with third party libraries
in tools/examples.

inv_txfm_add_16x16_adst_adst_0_12bpc_c: 8990.0
inv_txfm_add_16x16_adst_adst_0_12bpc_avx2: 646.1
inv_txfm_add_16x16_adst_adst_1_12bpc_c: 8965.3
inv_txfm_add_16x16_adst_adst_1_12bpc_avx2: 646.9
inv_txfm_add_16x16_adst_adst_2_12bpc_c: 8983.2
inv_txfm_add_16x16_adst_adst_2_12bpc_avx2: 870.1
inv_txfm_add_16x16_adst_dct_0_12bpc_c: 9058.2
inv_txfm_add_16x16_adst_dct_0_12bpc_avx2: 548.8
inv_txfm_add_16x16_adst_dct_1_12bpc_c: 9092.7
inv_txfm_add_16x16_adst_dct_1_12bpc_avx2: 549.3
inv_txfm_add_16x16_adst_dct_2_12bpc_c: 9086.7
inv_txfm_add_16x16_adst_dct_2_12bpc_avx2: 775.5
inv_txfm_add_16x16_adst_flipadst_0_12bpc_c: 9083.4
inv_txfm_add_16x16_adst_flipadst_0_12bpc_avx2: 645.6
inv_txfm_add_16x16_adst_flipadst_1_12bpc_c: 8998.3
inv_txfm_add_16x16_adst_flipadst_1_12bpc_avx2: 646.2
inv_txfm_add_16x16_adst_flipadst_2_12bpc_c: 9014.7
inv_txfm_add_16x16_adst_flipadst_2_12bpc_avx2: 873.8
inv_txfm_add_16x16_dct_adst_0_12bpc_c: 9080.1
inv_txfm_add_16x16_dct_adst_0_12bpc_avx2: 598.2
inv_txfm_add_16x16_dct_adst_1_12bpc_c: 9103.3
inv_txfm_add_16x16_dct_adst_1_12bpc_avx2: 598.1
inv_txfm_add_16x16_dct_adst_2_12bpc_c: 9089.5
inv_txfm_add_16x16_dct_adst_2_12bpc_avx2: 764.4
inv_txfm_add_16x16_dct_dct_0_12bpc_c: 1042.1
inv_txfm_add_16x16_dct_dct_0_12bpc_avx2: 28.6
inv_txfm_add_16x16_dct_dct_1_12bpc_c: 9164.6
inv_txfm_add_16x16_dct_dct_1_12bpc_avx2: 500.8
inv_txfm_add_16x16_dct_dct_2_12bpc_c: 9161.9
inv_txfm_add_16x16_dct_dct_2_12bpc_avx2: 678.2
inv_txfm_add_16x16_dct_flipadst_0_12bpc_c: 9104.9
inv_txfm_add_16x16_dct_flipadst_0_12bpc_avx2: 601.8
inv_txfm_add_16x16_dct_flipadst_1_12bpc_c: 9248.6
inv_txfm_add_16x16_dct_flipadst_1_12bpc_avx2: 599.2
inv_txfm_add_16x16_dct_flipadst_2_12bpc_c: 9087.4
inv_txfm_add_16x16_dct_flipadst_2_12bpc_avx2: 770.1
inv_txfm_add_16x16_dct_identity_0_12bpc_c: 6570.4
inv_txfm_add_16x16_dct_identity_0_12bpc_avx2: 243.9
inv_txfm_add_16x16_dct_identity_1_12bpc_c: 6615.4
inv_txfm_add_16x16_dct_identity_1_12bpc_avx2: 246.0
inv_txfm_add_16x16_dct_identity_2_12bpc_c: 6553.4
inv_txfm_add_16x16_dct_identity_2_12bpc_avx2: 435.0
inv_txfm_add_16x16_flipadst_adst_0_12bpc_c: 8982.1
inv_txfm_add_16x16_flipadst_adst_0_12bpc_avx2: 647.2
inv_txfm_add_16x16_flipadst_adst_1_12bpc_c: 8978.9
inv_txfm_add_16x16_flipadst_adst_1_12bpc_avx2: 647.2
inv_txfm_add_16x16_flipadst_adst_2_12bpc_c: 8964.0
inv_txfm_add_16x16_flipadst_adst_2_12bpc_avx2: 868.4
inv_txfm_add_16x16_flipadst_dct_0_12bpc_c: 9083.5
inv_txfm_add_16x16_flipadst_dct_0_12bpc_avx2: 550.0
inv_txfm_add_16x16_flipadst_dct_1_12bpc_c: 9070.4
inv_txfm_add_16x16_flipadst_dct_1_12bpc_avx2: 550.2
inv_txfm_add_16x16_flipadst_dct_2_12bpc_c: 9085.8
inv_txfm_add_16x16_flipadst_dct_2_12bpc_avx2: 779.7
inv_txfm_add_16x16_flipadst_flipadst_0_12bpc_c: 8977.1
inv_txfm_add_16x16_flipadst_flipadst_0_12bpc_avx2: 657.3
inv_txfm_add_16x16_flipadst_flipadst_1_12bpc_c: 9002.0
inv_txfm_add_16x16_flipadst_flipadst_1_12bpc_avx2: 657.3
inv_txfm_add_16x16_flipadst_flipadst_2_12bpc_c: 9008.4
inv_txfm_add_16x16_flipadst_flipadst_2_12bpc_avx2: 872.0
inv_txfm_add_16x16_identity_dct_0_12bpc_c: 6504.7
inv_txfm_add_16x16_identity_dct_0_12bpc_avx2: 387.5
inv_txfm_add_16x16_identity_dct_1_12bpc_c: 6548.3
inv_txfm_add_16x16_identity_dct_1_12bpc_avx2: 387.5
inv_txfm_add_16x16_identity_dct_2_12bpc_c: 6512.4
inv_txfm_add_16x16_identity_dct_2_12bpc_avx2: 387.5
inv_txfm_add_16x16_identity_identity_0_12bpc_c: 3926.2
inv_txfm_add_16x16_identity_identity_0_12bpc_avx2: 135.0
inv_txfm_add_16x16_identity_identity_1_12bpc_c: 3896.7
inv_txfm_add_16x16_identity_identity_1_12bpc_avx2: 134.5
inv_txfm_add_16x16_identity_identity_2_12bpc_c: 3888.0
inv_txfm_add_16x16_identity_identity_2_12bpc_avx2: 230.3

resize_8bpc_c: 542599.0
resize_8bpc_ssse3: 87635.4
resize_8bpc_avx2: 67401.1
resize_8bpc_avx512icl: 50263.6

resize_16bpc_c: 573438.9
resize_16bpc_ssse3: 121505.2
resize_16bpc_avx2: 83293.4
resize_16bpc_avx512icl: 77974.8

Allows to run most of dav1d_decode_frame_init unconditionally by putting the
CDF and subsequent initializations in a separate task.

This could cause a desync between first and cur, which results in
skipping a frame, halting the decoding.
This desync typically doesn't occur "long enough" in the current state of the
project to trigger the bug, as some frames would fix this cur back.
In order to trigger this, one needs to call reset_task_cur() on the last
frame, this would be the call post insertion of the INIT task (during
dav1d_task_frame_init).
This doesn't happen as we would normally pick a task from a previous frame
already in the queue.

(To be used alongside --filmgrain.)

Addresses part of #310.

Martin Storsjö authored 3 years ago and Ronald S. Bultje committed 3 years ago

This can't catch out of bounds reads (which is what caused the
crash in #380), but as long as reads and writes are properly matched,
it should catch the corresponding issues.

Martin Storsjö authored 3 years ago and Ronald S. Bultje committed 3 years ago

This is necessary if the dimensions set aren't properly aligned.

Martin Storsjö authored 3 years ago and Ronald S. Bultje committed 3 years ago

Before:                        Cortex A7      A8      A9     A53     A72     A73
mc_8tap_regular_w2_v_16bpc_neon:   384.4   194.0   242.9   193.2   134.1   140.0
mc_8tap_regular_w4_v_16bpc_neon:   578.2   242.2   282.7   263.1   171.2   168.9
After:
mc_8tap_regular_w2_v_16bpc_neon:   397.1   207.7   250.6   212.9   136.9   140.8
mc_8tap_regular_w4_v_16bpc_neon:   575.2   240.4   277.9   263.0   171.9   167.4

Martin Storsjö authored 3 years ago and Ronald S. Bultje committed 3 years ago

For 8tap, unroll the vertical filters slightly less (by 4 instead of
8 elements) and add a special case trailer that handles only 2 elements
(for 2x6 and 4x6). By unrolling less, performance on in-order cores is
somewhat impacted.

Before:                       Cortex A7      A8      A9     A53     A72     A73
mc_8tap_regular_w2_v_8bpc_neon:   340.0   305.4   336.5   196.5   160.5   167.8
mc_8tap_regular_w4_v_8bpc_neon:   400.4   319.5   391.5   210.3   189.7   188.8
After:
mc_8tap_regular_w2_v_8bpc_neon:   364.6   268.5   340.1   223.7   161.7   175.2
mc_8tap_regular_w4_v_8bpc_neon:   408.7   328.4   380.4   219.8   190.7   183.8